The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 08, 2000

Filed:

May. 21, 1997
Applicant:
Inventors:

Min-Liang Chen, Hsinchu, TW;

Chih-Hsun Chu, Hsinchu, TW;

Assignee:

Mosel Vitelic Inc., Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
438238 ; 438234 ; 438241 ; 438151 ; 438152 ; 438153 ; 438329 ; 438330 ; 438309 ; 438953 ; 438668 ;
Abstract

A method of making a resistor begins with forming a field effect transistor on a silicon semiconductor substrate. Then a first insulating layer is deposited on the field effect transistor. The first insulating layer is etched by the photolithography and etching techniques to form a bit line contact, and a bit line is subsequently formed. Next, upon the entire structure, a second insulating layer is formed and etched by the photolithography and ion etching techniques to form a contact hole with high aspect ratio. A polysilicon layer is deposited across the contact hole and the polysilicon outside the contact hole is removed, forming a polysilicon plug in the contact hole. Then, a third insulating layer is formed and etched to form a contact hole for metallurgy. After a first metal interconnection is formed, a third insulating layer is formed upon the entire structure and then etched to form a via hole by the photolithography and plasma etching techniques. A second metal interconnection is then formed and completes the static random access memory (SRAM) cell.


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