The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 08, 2000
Filed:
Oct. 02, 1997
Brian Michael Dowling, El Dorado Hills, CA (US);
James David Rodeo, Citrus Heights, CA (US);
Hewlett-Packard Company, Palo Alto, CA (US);
Abstract
A tool is provided that automates and expedites the ASIC design review process by allowing designers to perform a comprehensive asynchronous path design review of the circuit design HDL code. The tool operates on either an entire hierarchy or any sub-block of the circuit design. Filters are provided to allow the user to disregard known and desired synchronization circuits from the output generated by the tool. The tool provides an output that can take either of two formats, i.e. the output may be presented in a tabular form by hierarchical signal name, or it may be presented in a graphical, schematic block diagram form. In operation, the tool performs an exhaustive search of all circuits and identifies any asynchronous behavior. A user interface is provided that requires two data inputs and provides for an additional optional field. The two mandatory fields identify the location of all design files and the module at which the tool should begin its analysis. The tool begins its analysis at the level of the module input and traverses the circuit design from that point down the hierarchy to all end modules. Additional options and inputs govern the type and format of output information generated.