The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 08, 2000

Filed:

Mar. 02, 1998
Applicant:
Inventor:

Chun Jiang, San Jose, CA (US);

Assignee:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
716-1 ; 716-2 ; 326104 ; 326108 ; 326121 ;
Abstract

A system for simplifying and expediting estimation of the gate RC delay and/or the determination of transistor widths for a given gate RC delay in a CMOS inverter circuit. The system determines gate RC delay as a function of transistor width. Alternatively, appropriate transistor widths may be determined based on a desired optimum gate RC delay. An analytical expression is established to predict RC induced gate propagation delay as a function of readily available technical parameters in the early stage of design. The analytical expression has been found to describe gate RC delay in CMOS inverter circuits incorporating 0.25 micron (or even smaller) manufacturing technology.


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