The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 08, 2000
Filed:
Dec. 16, 1997
Kabushiki Kaisha Toshiba, Kawasaki, JP;
Abstract
Process simulation for LSIs and other semiconductor devices will handle plural same impurities introduced in different processes as different impurities. Thus, by handling them as different impurities in calculation, it is possible to obtain the distribution profiles of impurities in semiconductor devices without being effected by another same impurity introduced in another process or a number of processes during processing. With this, even a plurality of process conditions are discussed or when one or some of process(es) in a sequence of semiconductor device fabrication processes is (are) changed in procedure, it is not necessary to repeat the process simulation many times from the beginning. And it is possible to easily decide which process must be changed in conditions based on a finally obtained structure of semiconductor devices. The process simulation results are used directly as input to device simulation, to rapidly obtain performance of semiconductor devices such as current vs voltage characteristics. Therefore, the efficiency of calculations required to obtain the optimal conditions for semiconductor structures can be improved, thus shortening the lapse of time for designing and development of semiconductor devices.