The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 01, 2000

Filed:

Apr. 10, 1998
Applicant:
Inventors:

Daniel Lawrence Leibholz, Cambridge, MA (US);

Sven Eric Meier, Boston, MA (US);

James Arthur Farrell, Harvard, MA (US);

Timothy Charles Fischer, Maynard, MA (US);

Derrick Robert Meyer, Austin, TX (US);

Assignee:

Compaq Computer Corporation, Houston, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
712216 ; 712215 ; 712225 ; 714 48 ;
Abstract

A technique for speculatively issuing instructions using an out-of-order processor. A cache miss by a load instruction results in either a reissue of all subsequently issued instructions for an integer instruction stream, or a reissue of only truly dependent instructions for a floating point instruction stream. One version of the technique involves issuing and executing a first instruction, and issuing a second instruction during a speculative time window of the first instruction that occurs after the first instruction is issued. The technique further involves executing the issued second instruction when the first instruction is executed in a first manner, and reissuing the second instruction and executing the reissued second instruction when the first instruction is executed in a second manner that is different than the first manner.


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