The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 01, 2000

Filed:

Jul. 02, 1998
Applicant:
Inventor:

Steven J Yang, Hsinchu Hsien, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R / ;
U.S. Cl.
CPC ...
702118 ; 702108 ; 702117 ; 324519 ; 324537 ; 324754 ;
Abstract

A charge mode open/short test circuit comprises at least two charge capacitors. A plurality of signal traces under test are connected to the test circuit first through a plurality of test tips on a test prober and then a plurality of transmission gates in a test circuit. In a load mode, reference data are loaded. In a test mode, a charge capacitor is sequentially selected and discharged into the parasitic capacitor corresponding to a sequentially selected signal trace under test for generating a charge balance signal. The signal is amplified and compared with the loaded reference data in either a digital or an analog manner. The compared pass/fail output related to the property of the signal trace is stored in a memory. In a following read mode, the stored pass/fail output is read out to an external unit for further processing.


Find Patent Forward Citations

Yang, Steven. (2000). Charge mode open/short test circuit (U.S. Patent No. 6098027). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6098027

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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