The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 01, 2000
Filed:
Jun. 20, 1997
Kiyoshi Tateishi, Tsurugashima, JP;
Kazuo Takahashi, Tsurugashima, JP;
Pioneer Electronic Corporation, Tokyo, JP;
Abstract
The present invention is intended to reliably achieve a locked PLL even with a short VFO field to correctly perform subsequent reproduction of information data. A PLL circuit of the present invention is supplied with a composite signal composed of a repetitive signal including a pulse train of a constant duty ratio and a random signal including a pulse train allowing variations in duty ratio, where the two signals are arranged in time series. The circuit is provided with a VCO for generating an output signal having a frequency according to a control signal, a PFC for comparing the repetitive signal with the output signal in terms of phase and frequency to generate a phase frequency error signal, a PC for comparing the random signal with the output signal to generate a phase error signal, and loop filters for extracting predetermined band components of the phase frequency error signal and the phase error signal to generate the control signal. Since a PLL is formed including the phase frequency comparator, which has a wide dynamic range and operates at a single lock point, during reading a VFO, a reliable drawing operation is achieved even with a short VFO without miss lock.