The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 01, 2000

Filed:

Apr. 17, 1998
Applicant:
Inventors:

William Lo, Cupertino, CA (US);

Yi Cheng, San Jose, CA (US);

Bin Guo, Fremont, CA (US);

Assignee:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03D / ;
U.S. Cl.
CPC ...
375327 ; 375232 ; 375376 ;
Abstract

An optimum equalizer setting is determined for a signal equalizer in a network receiver by successively setting the equalizer to different predetermined settings, detecting timing correlation results between the equalized signal and a recovered clock in a digital phase locked loop, and determining a normalized distribution result for each of the predetermined equalizer settings based on the timing correlation results. The equalizer setting having the minimum normalized distribution result can then be selected as the optimum equalizer setting. Use of the correlation result from the phase locked loop enables the equalizer controller determining the optimum equalizer setting to determine the setting using a closed-loop setting. Hence, the equalizer controller can effectively determine the equalizer setting that causes the minimum amount of jitter in the phase locked loop.


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