The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 01, 2000

Filed:

Apr. 24, 1998
Applicant:
Inventors:

Shigeo Yamaguchi, Kanagawa, JP;

Junichi Horigome, Kanagawa, JP;

Takayoshi Chiba, Tokyo, JP;

Assignee:

Sony Corporation, Tokyo, JP;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11B / ;
U.S. Cl.
CPC ...
369 59 ;
Abstract

A structure for detecting a phase error for causing a PLL of an information reproducing apparatus to be locked and for selecting Viterbi determination mode, MSB determination mode (for obtaining a phase error detection timing corresponding to MSB of output data of an A/D converter disposed on the preceding stage of a Viterbi decoder) is disclosed. One of the three modes is selected corresponding to the state of the PLL. A Viterbi timing generating circuit, an MSB timing generating circuit, and a frequency lock mode timing generating circuit are provided. Phase error detection timings generated by the three circuits are selectively supplied to a phase error detecting circuit by a sampling pulse selecting switch. The selected phase error detection timing is switched between the acquisition mode and the tracking mode.


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