Integrated circuit memory devices including circuits and methods for

Abstract

An integrated circuit memory device includes a pair of bit lines, a memory cell array connected to the pair of bit lines, a pair of sensing bit lines and a switching unit that connects the pair of bit lines and the pair of sensing bit lines in response to an isolation control signal transmitted through an isolation control line. An equalizer equalizes the pair of bit lines in response to an equalization signal that is transmitted through an equalization control line. A sense amplifier senses and amplifies a voltage difference between the pair of sensing bit lines. A discharge circuit is connected between the isolation control line and a reference voltage such as ground, to discharge the isolation control line into the reference voltage in response to an inverted isolation control signal that is transmitted through a complementary line of the isolation control line. Preferably, the discharge circuit comprises a field effect transistor such as an NMOS transistor, the source and drain of which are connected between the isolation control line and the reference voltage and the gate of which is connected to the complementary line of the isolation control line.