The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 01, 2000

Filed:

Aug. 02, 1999
Applicant:
Inventors:

Antonin Rozsypal, Roznov, CZ;

Michael Zunino, Tempe, AZ (US);

Assignee:

Motorola, Inc., Schaumburg, IL (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ; H01L / ; H01L / ; H01L / ;
U.S. Cl.
CPC ...
257500 ; 257368 ; 257394 ; 257504 ;
Abstract

An arrangement (100) has a low voltage circuit (196') on a first doped well (110) and a high voltage circuit (197') on a second doped well (120) integrated into a common semiconductor substrate (105). The first well (110) laterally extends along a surface (106) of the substrate (105) to provide a voltage drop (.vertline.V.sub.LARGE .vertline.) between a first end (111) and a second end (112) so that potential differences between the circuits (196', 197') are substantially isolated. The low voltage circuit (196') controls a current from the second end (112) to provide a variable potential (by .vertline.V.sub.SMALL .vertline.) at the second end (112) which is communicated to other parts (193') of the second circuit (197') by a connection (150). The wells (110, 120) are spaced to provide isolation for potential magnitude changes between the second end (112) of the first well (110) and the second well (120) which are invoked by the first circuit (196').


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