The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 01, 2000
Filed:
Dec. 22, 1998
Applicant:
Inventors:
Chingchi Yao, Saratoga, CA (US);
Chung-Jen Chien, Saratoga, CA (US);
Thomas Chao, Cupertino, CA (US);
Assignee:
Oki Semiconductor, Sunnyvale, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
257296 ; 257532 ;
Abstract
A dynamic random access memory (DRAM) cell includes first and second MOS transistors, such as a PMOS transistor and NMOS transistor in a CMOS cell. One of the two transistors functions as a switch transistor while the other transistor is configured as a storage capacitor. The DRAM cell may be integrated into a logic device, such as a CMOS gate array, using PMOS and NMOS transistor cells formed in the gate array. In that case, the DRAM cell may be fabricated in a logic device with the standard processes used to produce the logic device.