The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 01, 2000

Filed:

Aug. 06, 1998
Applicant:
Inventors:

Thomas S Rupp, Stormville, NY (US);

Stephan Kudelka, Wappingers Falls, NY (US);

Jeffrey Gambino, Gaylordsville, CT (US);

Mary Weybright, Pleasant Valley, NY (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ;
U.S. Cl.
CPC ...
438981 ; 438275 ; 438279 ; 438296 ; 257390 ;
Abstract

A method for forming a pair of MOSFETs in different electrically isolated regions of a silicon substrate. Each one of the MOSFETs has a different gate oxide thickness. A first layer of silicon dioxide is grown to a predetermined thickness over the surface of the silicon substrate. One portion of the silicon dioxide layer is over a first isolated region and another portion of the silicon dioxide layer being over a second isolated region. An inorganic layer is formed over the silicon dioxide layer extending over the isolated regions of the silicon substrate. A first portion of the inorganic layer is over the first isolated regions and a second portion of the inorganic layer is over the second isolated regions. A photoresist layer is formed over the inorganic layer. The photoresist layer is patterned with a window over the first portion of the inorganic layer. The photoresist layer covers the second portion of the inorganic layer. The inorganic layer is patterned into an inorganic mask by bringing a etch into contact with the patterned photoresist layer to selectively remove the first portion of the inorganic layer an thereby expose an underlying portion of the surface of the silicon substrate while leaving the second portion of the inorganic layer. The inorganic mask is used to selectively remove exposed portions of the grown silicon dioxide. The inorganic mask is removed. A second layer of silicon dioxide is grown over the exposed underlying portion of the silicon substrate to a thickness different from the thickness of the first layer of silicon dioxide. The silicon dioxide layers are patterned into gate oxides for each of a corresponding one of the pair of MOSFETs.


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