Method and system for selective dram refresh to reduce power consumption

Abstract

A method and system for selective refresh for a memory array is disclosed. The method and system comprises providing a plurality of valid bits, each of the valid bits being associated with a row of the memory device; and detecting when data access is performed within a row of the device. The method and system further comprises setting the associated valid bit, the setting of the associated valid bit providing an indication that the row does not need to be refreshed for the refresh period. By providing the valid bits in the refresh controller and associating them with a row of the memory array then if a cell is written or read at least once a duration equivalent to a refresh period, then the cells do not need to be refreshed. When a DRAM cell is accessed (read or written), its charge is fully restored so that it does not need refresh for a duration equivalent to a refresh interval. In applications that use DRAMs to repeatedly write and read data, such as frame buffers in display systems, the DRAM cells may be accessed frequently enough so that the cells may not need to be refreshed at all. If the cells are written or read at least once in a duration equivalent to a refresh period, then they do not need to be refreshed. Accordingly, through the use of the present invention power consumption is significantly reduced.