The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 25, 2000
Filed:
Jul. 16, 1998
Kuang-Kai Chi, San Jose, CA (US);
Ping Xu, Milpitas, CA (US);
Seiko Epson Corporation, Tokyo, JP;
Abstract
A common mode logic (CML) circuit having an improved bias circuit and an active MOS load operating exclusively in the triode region to provide improved performance characteristics including a high speed of operation. The bias circuit of the CML circuit comprises a pair of MOS transistors, one of which has an aspect ratio (W.sub.P /L.sub.P) and the other of which has an aspect ratio (W.sub.P /L.sub.P)/n, wherein 1<n<4. This configuration causes a third MOS transistor in the bias circuit to operate exclusively in the triode region. The CML circuit also includes a logic portion, which may be a logic gate or flip-flop, having a plurality of pairs of input MOS transistors for receiving differential input signals. In accordance with the invention, the logic portion has load MOS transistors which operate exclusively in the triode region.