The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 25, 2000
Filed:
Aug. 03, 1996
David G Mavis, Albuquerque, NM (US);
Mission Research Corporation, Albuquerque, NM (US);
Abstract
A field programmable gate array has multiple logic units interconnected via level-0 routing structure to form tier 0 logic tiles. The level-0 routing structure has horizontal wiring and vertical wiring that is interconnected via a horizontal-to-vertical directional routing switch that transfers signals from the horizontal wiring to the vertical wiring. The tier 0 logic tiles are nested within and interconnected by a level-1 routing structure to form tier 1 logic tiles. The level-1 routing structure has horizontal wiring and vertical wiring that is interconnected via a vertical-to-horizontal directional routing switch that transfers signals from the vertical wiring to the horizontal wiring. The level-0 routing structure is also interconnected to the level-1 routing structure via inter-level routing switches. Signals traveling between any two logic units within a common tier 0 logic tile traverse at most one directional routing switch within the level-0 routing structure. As a result, the path delay between any two logic units is approximately equal and independent of the placement of the logic units within the tier 0 logic tile. Signals traveling between any two logic units in different tier 0 logic tiles traverse at most one directional routing switch within the level-1 routing structure and two inter-level routing switches. The path delay between any two logic units in different tiles is also approximately equal and independent of the placement of the logic units within the different tier 0 logic tiles. Additionally, the routing delays throughout the FPGA are independent of fanout of the routing net and independent of the number of wires used for the net.