The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 25, 2000

Filed:

Oct. 08, 1997
Applicant:
Inventors:

Koji Kishimoto, Tokyo, JP;

Yoshiaki Yamada, Tokyo, JP;

Assignee:

NEC Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
438624 ; 438626 ; 438631 ; 438669 ; 438763 ; 438778 ; 438787 ;
Abstract

A multi-layer interconnection structure in a semiconductor device has a interlevel dielectric layer of three SiO.sub.2 films. The first SiO.sub.2 film has a small thickness not lower than 25 nm and is formed by a dual-frequency plasma enhanced CVD process using alkoxysilane as a reactive gas. The second SiO.sub.2 film has a large thickness ranging between 300 and 800 nm and is formed on the first SiO.sub.2 film by an atmospheric pressure CVD process using a mixture of alkoxysilane and ozone as a reactive gas. The third SiO.sub.2 film has a thickness of 50 nm and is flattened by an etch-back process of the same together with an overlying sacrificial spin-on glass film. A second layer interconnect pattern is formed on or above the flattened third SiO.sub.2 film with an excellent reliability.


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