The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 25, 2000
Filed:
Feb. 26, 1998
Michael N Dillon, Richfield, MN (US);
LSI Logic Corporation, Milpitas, CA (US);
Abstract
A method of forming a layout definition of a semiconductor integrated circuit includes generating a netlist of functionally committed standard cell instances and the electrical interconnections between the standard cell instances. The standard cell instances are then placed in a layout pattern. Also, functionally uncommitted base cells are place with the standard cell instances in the layout pattern. The base cell instances may be metalized, if needed, in later processing steps to implement design changes by adding additional logical functions.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile