Robust interface for high speed memory access

Abstract

A memory interface for synchronous burst SRAMs is provided. In one embodiment, an information processing system comprises a processor and a memory coupled by a memory interface. The memory interface includes a left data latch and a right data latch. The left data latch latches and holds data provided by the memory until the processor accepts it. The right data latch latches and holds data provided by the memory if the left data latch is already latched. Each data latch is freed after its contents have been provided to the processor. A multiplexer is included to steer the least-recently latched data to the processor. The latches and multiplexer are controlled by an interface controller which tracks the state of the latches and the order in which they latched. The interface controller generates control signals in response to the state of the latches and signals from the processor and the memory. The memory interface advantageously operates to maintain the availability of addressed data from memory during interruptions of the processor so that no additional memory access cycles are lost when memory access is restarted by the processor.