Memory control unit using a programmable shift register for generating

Abstract

A programmable memory controller is described. The memory control signals and timings are defined by programmable means. A plurality of shift registers are loaded with programmed values at the start of a control sequence. The programmed values are synchronously shifted with the optimum value system clock to thereby generate a plurality of memory control signals. Each memory control signal is generated by a shift register. Depending on the mode of operation to be performed by the memory device, different programmed values are loaded into the plurality of shift registers at the start of a control sequence. The selection of which programmed value to be loaded into the plurality of shift registers is accomplished by a multiplexer device coupled with each shift register. The multiplexer device selects one input mode register containing programmed values. One input mode register exists for each mode of operation that can be performed by the memory device. The selected mode registers are loaded into each shift register to generate the desired control sequence for the memory device.