Crt update apparatus and method for variable size cache memory using

Abstract

A portion of cache memory may be converted from temporary memory to fixed memory such that the instructions, data or both instructions and data stored at the cache memory address are fixed or locked at the cache memory address and cannot be overwritten. As a result, the portion of the cache memory corresponding to the cache memory address becomes a physical static random access memory (SRAM). The cache memory has cache memory addresses with data elements temporarily stored therein and a tag associated with each cache memory address. A use mode selector designates whether the portion of cache memory located at the cache memory address is to be converted from temporary memory to fixed memory. A use mode cache controller, using an input address from a memory address register, a tag from a tag RAM portion of cache memory, and an upper limit address and lower limit address identifying the boundaries of the data in cache memory, determines whether the input address correctly corresponds to data stored in the data cache RAM portion of cache memory (i.e., whether the data corresponding to the input address is presently stored in cache memory). Thereafter, the use mode cache controller, based on the output of the use mode selector, converts the portion of the cache memory corresponding to the input address from temporary memory to fixed memory so that the data stored in such portion is fixed and cannot be overwritten. As a result, processor performance can be improved in that the demanded data resides permanently in cache memory thereby allowing decrease in access time without requiring increases in the size of cache memory.