Mechanism for synchronizing service of interrupts by a plurality of data

Abstract

An apparatus and method ensure that only one data processor, within a multiprocessor system, performs operations associated with an interrupt register having information corresponding to a particular interrupt. An interrupt register from a plurality of interrupt registers is selected via an address decoder, and data bits from the selected interrupt register are steered to a data bus. Each interrupt register has a corresponding trailing edge detector which clears the data content of the interrupt register after a first one of a plurality of data processors has read the data bits of that interrupt register on the data bus to service that particular interrupt. In this manner, a second one of the data processors which also attempts to service that particular interrupt reads the cleared content of that interrupt register. Upon reading the cleared content of that interrupt register, the second one of the data processors is alerted to return to a foreground task since that particular interrupt has already been serviced. The present invention also provides an option for not clearing an interrupt register. In addition, the present invention may include a mechanism for processing interrupt information data bit portions at a time by data type within an interrupt register.