Frequency synthesis architecture in a satellite receiver

Abstract

An improved DBS receiver front end architecture having a tuner chip and a demodulator/decoder chip. The tuner chip and the demodulator/decoder chip each include portions of a digital tuning frequency synthesizer. The frequency synthesizer comprises one or more digital counters which are implemented on the demodulator/decoder chip, and an oscillator which is implemented on the tuner chip. This advantageously avoids digital noise interference with the tuner chip while providing a reduced part count. Briefly, the present invention concerns a DBS receiver front end which includes a tuner chip and a demodulator/decoder chip which cooperate to perform a frequency synthesis function. The tuner chip has a tuning oscillator coupled to a tank circuit having an adjustable resonance frequency, and a downconverter coupled to receive a tuning frequency signal provided by the tuning oscillator. The demodulator/decoder chip has a programmable counter configured to count cycles of the tuning frequency to provide a frequency-divided signal to a phase detector. The phase detector compares the frequency-divided signal to a reference frequency, and is coupled to adjust the resonance frequency of the tank circuit to cause the tuning frequency to have a frequency which is a multiple of the resonance frequency. The demodulator/decoder chip also has a decoder which receives the baseband signal and converts it to a decoded signal.