Message box memory cell for two-side asynchronous access

Abstract

A new memory cell design having differential and dedicated read and write ports is disclosed. The memory cell utilizes separate write and read bit lines. The read bit lines are pre-charged to a first level. A grounding transistor is provided between the circuitry containing the cell's contents and the read bit lines such that the contents of the cell are isolated from the read bit lines. The grounding transistor is activated and deactivated by the data within the cell. The activation and deactivation of the grounding transistor causes the pre-charged bit lines to be pulled-down to a second level or to remain at the first level to accurately reflect the contents of the cell. Since the circuitry containing the contents of the cell is isolated from the read bit lines, a read operation on the cell will not interfere with an in progress write operation and thus, destruction of the cell's contents is prevented. In addition, the isolation prevents bit line coupling.