The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 18, 2000

Filed:

Jun. 23, 1998
Applicant:
Inventors:

Chester F Bassetti, Danville, CA (US);

Vincent Chor-Fung Yu, Sunnyvale, CA (US);

Assignee:

NeoMagic Corp., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G09G / ;
U.S. Cl.
CPC ...
345 87 ; 345 89 ;
Abstract

Frame acceleration is achieved by driving multiple LCD frames to a flat-panel display for each CRT frame. Rather than divide the flat-panel display into an upper and a lower half, the panel is divided into many segments. These are physical segments when the panel is row-addressable so that any segment can be accessed at any time. Virtual segments are used for standard dual-scan panels. A buffer memory receives gray-scale converted pixels and arranges them into segment-blocks. Multiple LCD frames are generated and stored using data acceleration. Frame-rate-cycling (FRC) of these multiple frames is used for gray-scaling. The size of the buffer memory is significantly reduced by organizing the frames into three or more segments since input and output timing can be overlapped, allowing lines to be sent to the panel at a higher rate than received by the buffer. While physical segments are most efficient, virtual segments still reduce memory requirements, especially when the multiple LCD frames are repeated. Standard progressive-scan panels benefit from less flicker and more accurate gray scaling with data acceleration. When data acceleration is combined with repeating frames, higher frame acceleration is achieved with low memory requirements.


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