Bias circuit for flash analog to digital converter circuits

Abstract

A bias circuit for a flash A/D converter having a first bus line and a second bus line includes a voltage reference operatively coupled to an operational amplifier circuit. The bias circuit further includes a first transistor, a second transistor, a first load resistor and a second load resistor. The collectors of the first transistor and second transistor are coupled to a supply voltage source through the first load resistor and second load resistor, respectively. The emitters of the first and second transistors are coupled to the first and second bus lines respectively. One of the first and second bus lines is coupled to the operational amplifier, providing a signal for negative feedback. A first current bypass circuit is coupled from the supply voltage source to the first bus line and provides a first current which is substantially equal to the quiescent current of the first bus line. A second current bypass circuit is coupled from the supply voltage source to the second bus line and provides a second current. The second current is less than the quiescent current of the second bus line by a magnitude substantially equal to the load current of one comparator attached to the bus lines. The voltage on the first bus line and second bus line are substantially equal and substantially constant. A differential voltage is developed across the collectors of the first transistor and the second transistor which is responsive to a change in current in the first and second bus lines.