The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 18, 2000
Filed:
Sep. 30, 1998
Applicant:
Inventors:
Mandeep Singh Chadha, Austin, TX (US);
Prabir C Maulik, Austin, TX (US);
Assignee:
Cirrus Logic, Inc., Fremont, CA (US);
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03M / ;
U.S. Cl.
CPC ...
341118 ; 341144 ; 341155 ;
Abstract
A technique for separating an operation of a digital stage into separate noise generation periods in order to time the generation of noise from the digital stage. The invention is utilized in a mixed-signal integrated circuit having analog and digital signals in which the timing of the noise generation ensures that noise is abated during an analog sampling event.
Chadha, Mandeep. (2000). Noise management scheme for high-speed mixed-signal integrated circuits (U.S. Patent No. 6091349). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6091349
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile