The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 18, 2000
Filed:
Sep. 19, 1997
Tushar R Gheewala, Los Altos, CA (US);
In-Chip Systems, Inc., Sunnyvale, CA (US);
Abstract
A layout architecture for routing local and global interconnections for a gate array integrated circuit wherein basic cells are arranged as an array with columns and rows. Local interconnection and global interconnections are routed on the first metal layer in a direction parallel to the rows (horizontal). Power supply signals and global interconnection are routed in the second metal layer in a direction parallel to the rows (horizontal). Global interconnections are routed on the third metal layer in a direction parallel to the columns (vertical).
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile