The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 18, 2000

Filed:

Dec. 22, 1997
Applicant:
Inventor:

Jae-Kap Kim, Ich'on, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
438228 ; 438199 ; 438231 ; 438232 ; 438225 ; 438227 ; 438203 ; 438201 ; 438209 ; 438200 ; 438358 ; 438328 ; 438529 ; 438268 ;
Abstract

Disclosed is a manufacturing method of semiconductor device which can simplify the manufacturing procedures for transistors with different gate insulation film thickness in the same substrate. According to the present invention, a manufacturing method for semiconductor device having NMOS and PMOS transistors with gate insulation films of different thickness from each other, is formed by the following processes. First, a semiconductor substrate in which a low voltage NMOS transistor region, a high voltage NMOS transistor region, a low voltage PMOS transistor region, and a high voltage PMOS transistor region are defined by isolation films, is provided. Next, a N well is formed in the low and high voltage PMOS transistor regions and threshold voltage adjustment ions for high voltage PMOS transistor are then implanted into the N well. Afterward, a P well is formed in the low and high voltage NMOS transistor regions and threshold voltage adjustment ions for low voltage NMOS transistor are then implanted into the P well. Next, a mask pattern exposing the high voltage NMOS transistor region and the low voltage PMOS transistor region is formed on the substrate. Threshold voltage adjustment ions for low voltage PMOS transistor are implanted into the exposed P well of the high voltage NMOS transistor region and the N well of the low voltage PMOS transistor region and the mask pattern is then removed. Next, a first gate insulation film is formed on the substrate and the first gate insulation film existing on the low voltage NMOS and PMOS transistors regions is removed. A second gate insulation film is then formed on the substrate.


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