The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 18, 2000
Filed:
Feb. 19, 1998
Vijayakumaran V Nair, Austin, TX (US);
Ronald D Holifield, Kyle, TX (US);
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
A method and apparatus for detecting floating transistor gates within a netlist model of an integrated circuit is disclosed. All transistor gates and input nodes coupled to the transistor gates are identified. These input nodes are then used to generate a resistor card. The resistor card is used in conjunction with the original netlist during simulation to couple two resistors to each input node. The first resistor is coupled between the input node and a high potential, and the second resistor is coupled between the input node and a lower potential. The resistors may be configured to have equal resistance values. The resistance values may be large enough to ensure that the current conducted through the resistors will be minimal in relation to the currents in the circuit when the input node is not floating. The resistance values may be small enough to overcome any leakage currents present in the circuit. The two resistors operate in combination to pull the input node to a voltage level near the midpoint between the higher and lower potentials. This midpoint voltage level turns on transistors having control terminals coupled to the input node and may consequently produces a relatively large current between the power supply and ground. This large current is easily detectable from the simulation output and may be used to locate which, if any, gates may have floating inputs that cause large static currents.