Synchronous data transfer system

Abstract

A synchronous data transfer system includes an oscillation circuit and a plurality of nodes connected to the oscillation circuit and each including at least an internal logic circuit. Each of the nodes outputs a phase reference signal indicating phase of the clock signal, data processed by the internal logic circuit provided internally of the node. The system further includes a transfer end signal indicating an end of the data transfer, in synchronism with the clock signal, and a phase reference signal bus connected to each of the plural nodes, a data bus connected to each of the plural nodes for transmitting the data and a transfer end signal bus connected to each of the plural nodes for transmitting the transfer end signal. A sender node of the plural nodes includes sending unit for sending the data to a receiver node of the plural nodes with a delay relative to the phase reference signal which the sender node itself sent onto the phase reference signal bus while sending simultaneously the transfer end signal to the receiver node, whereas the receiver node includes at least a selecting unit for converting the phase reference signal received into phase information to thereby select a clock signal having a predetermined phase with the clock signal received by the receiver node and a receiving unit for receiving the data from the sender node by using the selected clock signal.