The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 11, 2000
Filed:
Oct. 23, 1998
Sailesh Krishna Rao, Colts Neck, NJ (US);
Level One Communications, Inc., Sacramento, CA (US);
Abstract
A packetized trellis coder and method for providing error correction coding of IEEE 802.3 frame formatted Ethernet packets for transmission at one gigabit per second (Gbps) over twisted-pair wiring. The error correction code protects each byte of the ethernet frame with a parity bit constructed using a convolutional encoder such that a maximum likelihood sequence estimation at the receiver using a Viterbi decoder will result in a significant receiver performance gain. At the end of the Ethernet packet, the trellis coder restores the states of the convolutional encoder to a known value (state 0) before beginning Idle transmission so that the Viterbi decoder at the receiver can read off the end-of-packet symbols without any performance penalty. The mapping and the inverse mapping from raw data bits to symbols and vice-versa can be implemented with simple gates due to algorithmic symbol mapping of a 4-D trellis code via 1-D partitioning. The same redundancy that is needed for control code transmission in Ethernet frames is used to achieve the trellis coding and to improve receiver performance.