The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 11, 2000
Filed:
Jun. 27, 1997
Gary Feierbach, Belmont, CA (US);
Mukesh Patel, Fremont, CA (US);
Sun Microsystems, Inc., Palo Alto, CA (US);
Abstract
A microprocessor capable of performing multimedia and non-multimedia operations provided a plurality of stack based instructions is provided. The microprocessor includes a stack processor coupled to a stack capable of storing values, a register processor coupled to a register file capable of storing values, and a copy-unit having a first port coupled to the stack and a second port coupled to the register file being configured to copy data between the register file and the stack. The microprocessor also includes logic coupled to receive the plurality of stack based instructions from memory, cache, or other storage devices coupled to the microprocessor. The logic is configured to determine which of the plurality of stack based instructions are regular stack instructions and which of the plurality of stack based instructions are extended stack instructions. A stack decoder having a first port coupled to the logic and a second port coupled to the stack processor is configured to decode the regular stack instructions and provide control signals to the stack processor. A copy-unit decoder having a first port coupled to the logic and a second port coupled to the copy-unit is configured to decode extended stack instructions and provide control signals to the copy-unit. Further, a register processor decoder having a first port coupled to the logic and a second port coupled to the register processor is configured to decode extended stack instructions and provide the decoded extended stack instructions to the register processor.