The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 11, 2000

Filed:

Sep. 29, 1998
Applicant:
Inventor:

Carlos Munoz-Bustamante, Durham, NC (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ; G06F / ; H03K / ;
U.S. Cl.
CPC ...
710129 ; 710100 ; 326 56 ;
Abstract

A driver circuit includes both a conventional three state mode of operation and a five state operating mode. In the three state mode of operation, the output of the driver can be in logical 0 or logical 1 'voltage source' states, as well as a very high impedance state. In addition to these three states, the output of the driver in the five state mode of operation can also be in logical 1 and logical 0 'current source' states. The voltage source states are characterized by low output impedance (e.g., 30 Ohms), while the current source states are characterized by higher output impedance (e.g., 600 Ohms). The driver circuit is particularly useful for eliminating turnaround cycles on a multiplexed address/data bus. When coupled to such a bus, the clock line is used to select the voltage source mode during the first half of the clock cycle, and the current source mode during the last half of the clock cycle. Thus, two drivers that are coupled to the same line of the bus are prevented from being switched ON in the voltage source mode at the same time, which could otherwise occur momentarily during the transition from one clock cycle to the next.


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