Command queuing system for a hardware accelerated command interpreter

Abstract

A hardware implemented command queuing system in a hardware accelerated command interpreter engine. The command queuing system is an integral component of an autonomous hardware accelerated command interpreter type data processing engine that executes a programmable set of data processing commands in response to a stimulus from a host processor. The command queuing system is a configuration of registers and logic blocks that interact with a local host processor and other components within the command interpreter engine itself. The local host processor generates the commands to execute and the command queuing system queues the commands for seriatim execution by components within the command interpreter system. The command queue is a set of registers and command queue pointers that point to the next register available for writing a new command to the command queue, the next register that contains a command that is ready for executing, and the next register that contains the address of a completed command awaiting acknowledgment. The command queue pointers are managed by command queue interface control logic in the command queuing system. In the event of an error in executing any one command from the command queue, the command queuing system interacts with the local host processor to update the command queue pointers as needed to recover from the error and restart normal command queuing. The command queuing system also includes a set of control registers that contains internal command interpreter system operational status and local host processor accessible queuing and error status. The set of control registers are also managed by the command queue interface control logic in the command queuing system.