The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 11, 2000
Filed:
Jan. 30, 1998
Benjamin Jiann Hsu, San Jose, CA (US);
Aspec Technology, Inc., Sunnyvale, CA (US);
Abstract
The present invention provides a method and system for porting an integrated circuit layout from a reference process to a target process. The method and system comprises placing components related to the reference process on a grid, wherein the grid is determined by equations that are based upon the desired layout architecture. The method and system includes utilizing the design rules of the target process along with the equations to determine the grid of the target process. The component layout is controlled by parameters, where the design rules provide the values of the parameters. Thus, each component will be properly ported when the parameter values are changed to that of the target process. Finally, the locations of the components are mapped grid-point to grid-point from the reference process to the target process. In so doing, an integrated circuit layout in the target process is drawn without design rule violation.