Read only memory capable of realizing a high-speed read operation

Abstract

A read-only memory device having a NOR structure is provided. The memory device comprises a memory cell array having a plurality of memory cells, each memory cell storing data, a plurality of first bit lines coupled to the array, and a plurality of second bit lines coupled to the array. A first selection circuit are coupled to the plurality of first bit lines for selecting at least two adjacent first bit lines. A second selection circuit coupled to the plurality of second bit lines for selecting at least two adjacent second bit lines. A sense amplification circuit detect a cell state of a selected memory cell by biasing the selected first bit lines and one of the selected second bit lines with a same potential. The second selection circuit grounds another of the selected second bit lines. The first selection circuit grounds unselected first bit lines and wherein the second selection circuit grounds unselected second bit lines. According to the mask ROM of the present invention, leakage current paths to the biased main and ground bit lines are cut off during a data reading operation of an off-cell. The biased main and ground bit lines can be charged by only one sense amplification circuit.