The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 11, 2000
Filed:
Dec. 23, 1997
John Gordon Hogeboom, Nepean, CA;
Nortel Networks Corporation, Montreal, CA;
Abstract
A delay circuit for delaying high-speed logic signals has a continuously-variable delay which is a linear function of a control current. The resulting delay time may be set as short as a single logic gate delay. The CMOS delay circuit comprises delay means having as its output an internal signal characterized by an internal signal swing, coupled to amplifier means whose output is the delayed logic signal, characterized by a settling time. The amplifier means contributes minimal delay. The swing of the internal signal of the delay circuit is controlled by differential negative feedback to be just sufficient to drive the next stage, while the delay circuit's settling time is controlled by capacitively coupled positive feedback to be as short as the delay itself. The differential negative feedback is provided by four MOS devices.