Metal interconnect stack for integrated circuit structure

Abstract

A metal interconnect stack for an integrated circuit structure is described comprising a main metal interconnect layer, an underlying TiN barrier layer and a titanium metal seed layer below the TiN barrier layer, and a barrier layer below the titanium metal seed layer to provide protection against chemical interaction between the titanium metal seed layer and an underlying plug in a via. The structure is formed by providing an integrated circuit structure having an insulation layer formed thereon with one or more metal-filled vias or contact openings generally vertically formed therethrough to have an upper surface thereon; forming a lower barrier layer such as a TiN barrier layer over the insulation layer and the upper surface of the metal in the one or more metal-filled vias; and subsequently forming the titanium seed layer over the lower TiN barrier layer. This new first TiN barrier layer then separates the surface of the metal in the one or more vias from the titanium seed layer in the metal interconnect stack to inhibit galvanic action between the metal in the one or more vias and the titanium seed layer. Preferably, the main metal interconnect layer is provided with a <111> crystallographic orientation to enhance the electron migration of the main metal interconnect layer. To achieve this <111> orientation in the main metal interconnect layer, the main titanium nitride barrier layer is preferably also provided with <111> crystallographic orientation and the titanium metal seed layer functions as a seed layer for the second TiN barrier layer which will, in turn, act as a seed layer for the main metal interconnect layer. An optional third TiN barrier layer may be formed over the main metal interconnect layer.