Method for design implementation of routing in an fpga using placement

Abstract

A method of computer aided design of coarse grain FPGA's by employing a library of selected primitive cells, defining the connection classes useful in the FPGA design, and assigning appropriate connection classes to the inputs and outputs of the respective primitive cells. The primitive cells and defined interconnections used therein have accurately established timing and power parameters thereby enabling more accurate assessments of static timing and power consumption for the entire FPGA design. Moreover, the method of the present invention results in placement directives which then serve as connection criteria in carrying out subsequent place and route algorithms. One such placement directive is implemented as a 'local output' (LO) of some of the primitive cells which implies that that particular output must be connected to another primitive cell input within the local configurable logic block (CLB). Another such placement directive is obtained by using a plurality of virtual buffers. They're referred to as virtual buffers because they serve only a design function and do not actually exist in a CLB. The virtual buffers provide placement directives such as to connect a primitive cell output to another CLB input within some prescribed geographical limit such as within 4 or 6 CLBs of the one in which the buffer is 'located'.