The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 04, 2000

Filed:

Apr. 21, 1998
Applicant:
Inventors:

Hideki Mizuno, Tokyo, JP;

Mitsunori Kanemoto, Tokyo, JP;

Assignee:

NEC Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
257779 ; 257692 ; 257696 ; 257735 ;
Abstract

In a semiconductor device, each of a plurality of leads has a chip mounting portion electrically connected to the semiconductor chip through a bump and a lead main body supporting the chip mounting portion. A lead path from the distal end of the lead main body to the bump is bent in X, Y, and Z directions so that the distal end portion of the lead main body and the chip mounting portion are arranged on different levels when viewed from a side surface. The lead main body and the chip mounting portion substantially make a right angle to form an L shape when viewed from an upper side. The semiconductor chip is connected, through bumps, to upper surfaces of distal end portions of the chip mounting portions of the leads on a plane. A molded body seals constituent elements except a part separated from a connection portion between the lead main body and the chip mounting portion, and incorporates a bent portion of the lead main body. Each lead is arranged such that the chip mounting portions are arranged on both sides of a centerline of the semiconductor device in a longitudinal direction to be parallel to the centerline. The L-shaped leads are arranged on one side such that the chip mounting portions oppose each other on a plane. A lead frame and lead bonding are also disclosed.


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