The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 04, 2000
Filed:
Jan. 05, 1998
Seok Ho Kang, Incheon-si, KR;
Kuk Jin Chun, Seoul, KR;
LG Semicon Co., Ltd., Chungcheongbuk-do, KR;
Abstract
A field emission device includes a field emission cathode electrode having a cusp, a first insulating layer on the field emission cathode electrode excluding a portion over the cusp, a first electrode on the first insulating layer, a second insulating layer on the first electrode, a second electrode on the second insulating layer, a third insulating layer on the second electrode, and a silicon substrate on the third insulating layer. A method of fabricating a field emission device having a semiconductor substrate includes the steps of sequentially forming first and second insulating layers on first and second surfaces of the substrate, removing the first and the second insulating layers from the first surface of the substrate, forming a third insulating layer and a first metallic layer on the first surface of the substrate, selectively removing the first insulating layer and the second insulating layer on the second surface of the semiconductor substrate to expose the substrate, forming a fourth insulating layer and a second metallic layer on the first metallic layer, forming a hole trench to expose the third insulating layer, forming a fifth insulating layer over an exposed front surface including the hole trench, forming a third metallic layer on the fifth insulating layer, anisotropically etching the silicon substrate from the second surface to expose the fifth insulating layer through the hole trench, and removing the fifth insulating layer in the hole trench.