Method and apparatus for generating a clock signal from a plurality of

Abstract

A PLL circuit for selecting a clock signal from among a plurality of clock signals having different phases is disclosed. The PLL circuit includes a selector for selecting at least one of the plurality of clock signals. Duty cycle distortion is avoided by ensuring that at least one of the clock signals is always selected to drive the output of the PLL circuit, P.sub.out. In one implementation, at least two of the clock signals are selected at a given time, so that at least one of the selected signals is always driving the output during a transition from one set of selected clock signals to another set of selected clock signals. In another implementation, the selector activates a desired clock signal before deactivating the currently selected clock signal, so that at least one of the clock signals is always selected. More than two phases can be simultaneously selected, for example, if there is a large capacitive load on the output signal, P.sub.out. The PLL circuit can be programmed to select only one clock phase at lower clock speeds.