Processor having a scalable, uni/multi-dimensional, and

Abstract

A processor is implemented with an operand register file having N operand registers, instructions that reference these operand registers with virtual and physical source and destination addresses of variable up to n addressing dimensions, and at least one address mapping circuit that maps the uni-dimensional virtual and the multi-dimensional virtual/physical source and destination addresses to their uni-dimensional equivalents. Whether a source/destination address is a virtual or a physical address may be implicitly inferred from the instruction type, or explicitly specified. Source and destination addresses of an instruction may be either all virtual addresses, or all physical addresses, or virtual as well as physical addresses. The addressing dimension of an instruction's source and destination addresses may be specified in the instruction, or specified in a control register of the processor. All portions of a virtual/physical source/destination address may be specified in an instruction, or some portions are specified through control registers of the processor. As a result, various upward compatible embodiments, scaled to various performance design points suitable for multi-scalar, vector, and/or multi-processing, as well as software pipelined load, calculate, and store processing can be created.