The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 27, 2000
Filed:
Sep. 25, 1998
Mike Lowe, Austin, TX (US);
Paul Berndt, Austin, TX (US);
Tahsin Askar, Austin, TX (US);
Enrique Rendon, Pflugerville, TX (US);
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
A system and method for dynamic verification of functionality of an HDL (Hardware Description Language) design of a computer system component is disclosed. A simulated model of the HDL design is created. A test configuration for the simulated model is selected through a configuration interpretation mechanism, based on a plurality of user-supplied parameters. The user-supplied parameters, for example, include the amount of the memory in the system, the number of memory banks, addresses of various PCI devices, the type of the CPU etc. The test configuration is then compiled. At run-time, the test configuration is simulated. The responses by the simulated model of the HDL design to various test stimuli from a stimulus file are then evaluated under the chosen test configuration. One or more different test configurations may be simulated at run-time, and the stimulated model's responses to a pre-determined set of test stimuli may be reevaluated for each such test configuration. Thus, the test configuration is effectively separated from the test stimulus generation mechanism. This allows permutations of a given test suite across many test configurations without creating extremely large number of tests.