The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 27, 2000
Filed:
Jun. 19, 1998
Stephen C Purcell, Mountain View, CA (US);
Nital P Patwa, San Jose, CA (US);
ATI International SRL, , BB;
Abstract
A multiplier has two input value terminals which receive two signed input bit groups. The multiplier also has two output terminals configured to carry a sum and carry bit group representing, in redundant form, a product of the two signed input values. A sign determining circuit generates a sign bit representing a sign of the product of the two input signed values. An extension unit has three input terminals configured to receive the most significant bit of the sum bit group, the most significant bit of the carry bit group, and the sign bit generated by the sign determining circuit. The extension unit is structure to generate a least significant extension bit and a more significant extension bit. The least significant extension bit has one binary state if the sum most significant bit, the sign bit, and the carry most significant bit have the same binary state. The least significant extension bit otherwise has the opposite binary state.