The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 27, 2000
Filed:
Jul. 11, 1996
John Philip Bolash, Lexington, KY (US);
Thomas Jon Eade, Lexington, KY (US);
Mark Joseph Edwards, Lexington, KY (US);
Bruce David Gibson, Lexington, KY (US);
Lexmark International, Inc., Lexington, KY (US);
Abstract
Method and apparatus for inhibiting electrically induced ink build-up on flexible, integrated circuit connecting leads, for thermal ink jet printer heads is disclosed, and relates to a thermal ink jet printer having a print head comprising an integrated circuit chip, a nozzle plate including a plurality of ink ejecting nozzles therein and overlying a heater resistor for each of the nozzles. Each of the associated heater resistors has associated active circuitry on the chip. On the chip there are a plurality of auxiliary functions requiring power, for example a substrate (silicon chip) heater, a shift register containing print head identification, fault detection circuit connections, etc. The machine includes a power supply and printer control logic, and gate means responsive to the logic upon sending a control signal to effect operation of at least one of the auxiliary functions to energize the function by gating the power supply to the integrated circuit chip and the associated auxiliary function only for a duration corresponding to necessary energization of the function. Because electrically induced ink build-up (EIIBU) usually occurs only between adjacent lands or traces of the TAB or flexible printed circuit that have voltage differentials, functions associated with those lands or traces are the functions which are gated to power from the power supply.