The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 27, 2000
Filed:
Oct. 02, 1998
Reading Maley, San Francisco, CA (US);
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
An output buffer interfaces a digital system having devices designed for low operating voltages to an output coupled to an external system having higher operating voltages. The output buffer drives the output to one of a high output voltage and a low output voltage while limiting voltage across terminals of devices within the output buffer. The output buffer includes a pull-up stack of a first plurality of devices, coupled between a high power supply and the output, which turn on when the output is driven to the high output voltage and which turn off when the output is driven to the low output voltage. The voltage difference between the output and the high power supply is distributed across the first plurality of devices when the output is driven to the low output voltage. The output buffer further includes a pull-down stack of a second plurality of devices, coupled between a low power supply and the output, which turn on when the output is driven to the low output voltage and which turn off when the output is driven to the high output voltage. The voltage difference between the output and the low power supply is distributed across the second plurality of devices when the output is driven to the high output voltage. The output buffer further includes a clamping circuit, coupled to the output and to a predetermined node of the first and second plurality of devices, for limiting voltage across terminals of each of the first and second plurality of devices by discharging down the predetermined node when the output is driven to the low output voltage and by charging up the predetermined node when the output is driven to the high output voltage.