The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 27, 2000
Filed:
Mar. 27, 1995
LSI Logic Corp., Milpitas, CA (US);
Abstract
A repeating cell structure in a semiconductor substrate for a BiCMOS logic gate array. The cell structure has three regions shaped as columns. The first columnar region is a P-well and has four vertically aligned active areas of N-type material formed within the columnar region. Each of the active areas has two gate electrodes to form two NMOS transistors. Similarly the second columnar region is a N-well and has four vertically aligned active areas of P-type material. Each such active region forms two PMOS transistors. The third column has two bipolar transistors, each with collector, base and emitter regions vertically aligned. The resulting BiCMOS logic array permits a flexible location of macrocells, which results in a compact implementation of the resulting integrated circuit.