Word line voltage supply circuit

Abstract

An address transition detector (ATD) detects a change of address and generates a pulse signal Sc. A control circuit generates a pulse signal Sd and outputs it to a booster circuit in response to a timing of completion of the signal Sc. The booster circuit generates a boosted voltage higher in level than a power supply voltage during an active period of the signal Sd and outputs it to a decoder. The decoder holds the control gate of the output transistor connected to the word line selected in response to the address at a first voltage level, then inputs the boosted voltage to one of the source and drain electrodes so as to hold the gate at a second voltage level higher than the first voltage level by exactly the boosted voltage using capacitive coupling between the control gate and the one of the source and drain electrodes, whereby it outputs a boosted voltage to the other of the drain and source electrodes and drives the word line connected to the other of the drain and source electrodes. Since a boosted voltage higher than the power supply voltage is supplied to the selected word line, the write operation can be carried out reliably and deterioration of the data holding characteristic of the memory cell due to the reduction of the power supply voltage can be prevented.